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?2010 f airchild semiconductor corporation fdb045an08a0_f085 rev. a ww w.fairchildsemi.com fdb045an08a0 _ f085 n-channel powertrench ? mosfet fdb045an08a0 f085 n-channel powertrench ? mosfet 75v, 80a, 4.5m features ?r ds(on) = 3.9m (typ.), v gs = 10v, i d = 80a ?q g (tot) = 92nc (typ.), v gs = 10v ? low miller charge ? low q rr body diode ? uis capability (single pulse and repetitive pulse) ? qualified to aec q101 formerly developmental type 82684 applications ? 42v automotive load control ? starter / alternator systems ? electronic power steering systems ? electronic valve train systems ? dc-dc converters and off-line ups ? distributed power architectures and vrms ? primary switch for 24v and 48v systems mosfet maximum ratings t c = 25c unless otherwise noted symbol parameter ratings units v dss drain to source voltage 75 v v gs gate to source voltage 20 v i d drain current 90 a continuous (t c < 137 o c, v gs = 10v) continuous (t amb = 25 o c, v gs = 10v, with r ja = 43 o c/w) 19 a pulsed figure 4 a e as single pulse avalanche energy (note 1) 600 mj p d power dissipation 310 w derate above 25 o c 2.0 w/ o c t j , t stg operating and storage temperature -55 to 175 o c thermal characteristics r jc thermal resistance junction to case to-263 0.48 o c/w r ja thermal resistance junction to ambient to-263 (note 2) 62 o c/w r ja thermal resistance junction to ambient to-263, 1in 2 copper pad area 43 o c/w this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certification. d g s to-263ab fdb series gate source drain (flange) ? rohs compliant june 20 10 _
f db045an08a0_f085 rev. a www.fairchildsemi.com package marking and ordering information d evice marking device package reel size tape width quantity fdb045an08a0 fdb045an08a0_f085 to-263ab 330mm 24mm 800 units electrical characteristics t c = 25c unless otherwise noted symbol parameter test conditions min typ max units of f characteristics b vdss dr ain to source breakdown voltage i d = 250 a, v gs = 0v 75 - - v i dss z ero gate voltage drain current v ds = 60v - - 1 a v gs = 0v t c = 150 o c - - 250 i gss gate to sour ce leakage current v gs = 20v - - 100 na on cha racteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a2-4v r ds (on) dr ain to source on resistance i d = 80a, v gs = 10v - 0.0 039 0.0045 i d = 37a, v gs = 6v - 0.0 056 0.0084 i d = 80a, v gs = 10v, t j = 175 o c - 0.0 08 0.011 dynamic characteristics c iss inpu t capacitance v ds = 25v, v gs = 0v, f = 1mh z - 6600 - pf c oss output c apacitance - 1000 - pf c rss rever se transfer capacitance - 240 - pf q g(tot) t otal gate charge at 10v v gs = 0v to 10v v dd = 40v i d = 80a i g = 1.0ma 92 138 nc q g( th) t hreshold gate charge v gs = 0v to 2v - 11 17 nc q gs gate to source gate charge - 27 - nc q gs2 gate cha rge threshold to plateau - 16 - nc q gd gate to d rain miller charge - 21 - nc swit ching characteristics (v gs = 10v) t on turn-on time v dd = 40v, i d = 80a v gs = 10v, r gs = 3. 3 - - 160 ns t d( on) tu rn-on delay time - 18 - ns t r rise time - 88 - ns t d(off) t urn-off delay time - 40 - ns t f fa ll time - 45 - ns t off tu rn-off time - - 128 ns drain-source diode characteristics v sd sour ce to drain diode voltage i sd = 80a - - 1.25 v i sd = 40a - - 1. 0v t rr revers e recovery time i sd = 75a, d i sd /dt = 100a/ s- - 53ns q rr rever se recovered charge i sd = 75a, d i sd /dt = 100a/ s- - 54nc notes: 1: starting t j = 25c, l = 0.48mh, i as = 50a. 2: pulse width = 100s fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085a rev. a www.fairchildsemi.com typical characteristics t c = 25 c unless otherwise noted figure 1. t c , case temperature ( o c) power dissipation multiplier 0 0255075100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 normalized power dissip ation vs ambient temperature figure 2. 0 40 80 120 160 200 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) current limited by package maximum continuous drain current vs case temperature figure 3. 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse nor malized maximum transien t thermal impedance figure 4. 100 1000 2000 50 i dm , peak current (a) t, pulse width (s) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 transconductance may limit current in this region v gs = 10v t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: peak current capability fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com figure 5. 0.1 1 10 100 1000 0.1 1 10 100 2000 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c single pulse limited by r ds (on) area may be operation in this 10 s 10ms 1ms dc 100 s forward bias safe operating area note: refer to fairchild application notes an7514 and an7515 fi gure 6. 1 10 100 .01 0.1 1 10 100 500 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv ds s - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv ds s - v dd ) +1] u nclamped inductive switching capability figure 7. 0 30 60 90 120 150 4.04.55.05.56.0 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c t ransfer characteristics figure 8. saturation characteristics 0 30 60 90 120 150 00.51.01.5 i d , drain current (a) v ds , drain to source voltage (v) v gs = 6v pulse duration = 80 s duty cycle = 0.5% max v gs = 5v t c = 25 o c v gs = 10v v gs = 7v fi gure 9. 3 4 5 6 7 0 20406080 i d , drain current (a) v gs = 6v v gs = 10v drain to source on resistance(m ) pulse duration = 80 s duty cycle = 0.5% max drain to source on resistance vs drain current figure 10. 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d =80a pulse duration = 80 s duty cycle = 0.5% max n ormalized drain to source on resistance vs junction temperature typical characteristics t c = 25 c unless otherwise noted fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com figure 11. 0.4 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 200 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage normalized gate threshold voltage vs junction temperature figure 12. 0.90 0.95 1.00 1.05 1.10 1.15 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage normalized drain to source breakdown voltage vs junction temperature figure 13. 100 1000 10000 0.1 1 10 75 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss c gs + c gd c oss c ds + c gd c rs s c gd c apacitance vs drain to source voltage figure 14. 0 2 4 6 8 10 0255075100 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 40v i d = 80a i d = 10a waveforms in descending order: ga te charge waveforms for constant gate currents typical characteristics t c = 25 c unless otherwise noted fdb045an08a0 _ f085 n-channel powertrench ? mosfet
test circuits and waveforms fi gure 15. t p v gs 0.01 l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v un clamped energy test circuit figure 16. v dd v ds bv dss t p i as t av 0 unc lamped energy waveforms figure 17. v gs + - v ds v dd dut i g(ref) l gate charge test circuit figure 18. v dd q g( th) v gs = 2v q gs2 q g(t ot) v gs = 10v v ds v gs i g( ref) 0 0 q gs q gd gate charge waveforms figure 19. v gs r l r gs dut + - v dd v ds v gs switching time test circuit figure 20. t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 switching time waveforms f db045an08a0_f085 rev. a www.fairchildsemi.com fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. t herefore the applications ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be review ed to ensure that t jm is never exce eded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. (eq. 1) 3 '0 7 -0 7 $ C
5 -$ -- ------------------------ = in using surface mount devices such as the to-263 package, the environment in which it is applied will have a significant influence on the parts current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designers preliminary application evaluation. figure 21 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 21 or by calculation using equation 2 or 3. equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. the area, in square inches or square centimeters is the top copper area including the gate and source pads. area in inches squared (eq . 2) 5 -$ $uhd +
-------------------------------------- - + = (eq . 3) 5 -$ $uh d +
---- ------------------------------- - + = area in centimeter squared f igure 21. thermal r esistance vs mounting pad area 20 40 60 80 110 0.1 r ja = 26.51+ 19.84/(0.262+area) eq.2 r ja ( o c/w) area, top copper area in 2 (cm 2 ) (0.645) (6.45) (64.5) r ja = 26.51+ 128/(1.69+area) eq.3 fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com pspice electrical model . subckt fdb045an08a0 2 1 3 ; rev march 2002 ca 12 8 1.5e-9 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 cb 15 14 1.5e-9 cin 6 8 6.4e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 82.3 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 4.81e-9 lsource 3 7 4.63e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 9e-4 rgate 9 20 1.36 rldrain 2 5 10 rlgate 1 9 48.1 rlsource 3 7 46.3 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 2.3e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v( 5,51)))*(pwr(v(5,51)/( 1e-6*250),10))} .model dbodymod d (is = 2.4e-11 n = 1.04 rs = 1.76e-3 trs1 = 2.7e-3 trs2 = 2e-7 xti=3.9 cjo = 4.35e-9 tt = 1e-8 m = 5.4e-1) .model dbreakmod d (rs = 1.5e-1 trs1 = 1e-3 trs2 = -8.9e-6) .model dplcapmod d (cjo = 1.35e-9 is = 1e-30 n = 10 m = 0.53) .model mmedmod nmos (vto = 3.7 kp = 9 is =1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.36) .model mstromod nmos (vto = 4.4 kp = 250 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 3.05 kp = 0.03 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.36e1 rs = 0.1) .model rbreakmod res (tc1 = 1.05e-3 tc2 = -9e-7) .model rdrainmod res (tc1 = 1.9e-2 tc2 = 4e-5) .model rslcmod res (tc1 = 1.3e-3 tc2 = 1e-5) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -6e-3 tc2 = -1.9e-5) .model rvtempmod res (tc1 = -2.4e-3 tc2 = 1e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.0 voff= -1.5) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.5 voff= -4.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= -1.0) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com saber electrical model rev ma rch 2002 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 te mplate fdb045an08a0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, n1 = 1.04, rs = 1.76e-3, trs1 = 2.7e-3, trs2 = 2e-7, xti = 3.9, cjo = 4.35e-9, tt = 1e-8, m = 5.4e-1) dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 1.35e-9, isl =10e-30, nl =10, m = 0.53) m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0) c.ca n12 n8 = 1.5e-9 c.cb n15 n14 = 1.5e-9 c.cin n6 n8 = 6.4e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.81e-9 l.lsource n3 n7 = 4.63e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -9e-7 res.rdrain n50 n16 = 9e-4, tc1 = 1.9e-2, tc2 = 4e-5 res.rgate n9 n20 = 1.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 48.1 res.rlsource n3 n7 = 46.3 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -6e-3, tc2 = -1.9e-5 spe.ebreak n11 n7 n17 n18 = 82.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } } fdb045an08a0 _ f085 n-channel powertrench ? mosfet
f db045an08a0_f085 rev. a www.fairchildsemi.com spice thermal model rev 23 m arch 2002 fdb045an08a0t ctherm1 th 6 6.45e-3 ctherm2 6 5 3e-2 ctherm3 5 4 1.4e-2 ctherm4 4 3 1.65e-2 ctherm5 3 2 4.85e-2 ctherm6 2 tl 1e-1 rtherm1 th 6 3.24e-3 rtherm2 6 5 8.08e-3 rtherm3 5 4 2.28e-2 rtherm4 4 3 1e-1 rtherm5 3 2 1.1e-1 rtherm6 2 tl 1.4e-1 saber thermal model saber therma l model fdb045an08a0t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.65e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 1e-1 rtherm.rtherm1 th 6 = 3.24e-3 rtherm.rtherm2 6 5 = 8.08e-3 rtherm.rtherm3 5 4 = 2.28e-2 rtherm.rtherm4 4 3 = 1e-1 rtherm.rtherm5 3 2 = 1.1e-1 rtherm.rtherm6 2 tl = 1.4e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case fdb045an08a0 _ f085 n-channel powertrench ? mosfet
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